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发明名称
LOGIC CIRCUIT VERIFYING METHOD
摘要
申请公布号
JPH0676015(A)
申请公布日期
1994.03.18
申请号
JP19920160581
申请日期
1992.06.19
申请人
SHARP CORP
发明人
TOYODA TADAO
分类号
G06F11/25;G06F11/26;G06F17/50;(IPC1-7):G06F15/60
主分类号
G06F11/25
代理机构
代理人
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地址
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