发明名称 SEMICONDUCTOR MEMORY
摘要 PURPOSE:To test the device in a short time while preventing the increase of the number of pins in a semiconductor memory device capable of storing plural bits in the same address. CONSTITUTION:Circuits 112, 114, 116, 118 for detecting the coin-match or unmatch or respective data are provided between data read out of the same address in plural memory cell blocks and input/output pins D01-D04 used for ordinary reading and writing of data. Preferably, a logical circuit 120 for superposing the outputs of the circuits 112, 114, 116, 118 is provided. An error flag signal outputted from the superposing logic circuit 120 is e.g. outputted from an unused pin 64.
申请公布号 JPH0676598(A) 申请公布日期 1994.03.18
申请号 JP19920230455 申请日期 1992.08.28
申请人 MITSUBISHI ELECTRIC CORP 发明人 FUDEYASU YOSHIO
分类号 G11C29/00;G11C29/12;G11C29/14;G11C29/28;(IPC1-7):G11C29/00 主分类号 G11C29/00
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