| 摘要 |
<p>PURPOSE: To maintain an always optimal interface state by changing a clock cycle by generating a slow signal at the time of interfacing with a peripheral circuit, and holding the operation of a system controller while a waiting signal is active at the time of operating after receiving a ready signal. CONSTITUTION: An address decoding circuit 100 generates a slow signal by decoding the address of a peripheral circuit whose operating frequency is slow, and forcedly delays the clock frequency of a clock generating circuit 200. The clock generating circuit 200 is constituted of three delaying parts having plural AND gates, plural NOR gates which receive the outputs of the AND gates, and plural flip flops which receive the outputs of the NOR gates. Thus, an always optimal interface state can be maintained.</p> |
