| 摘要 |
PURPOSE:To obtain a burst converting circuit which is sure and efficient with time, by performing frame matching by using a vacant time slot from the moment when a data signal train is read out in a burst-like condition to the moment at which signal readout is again started in a burst-like condition. CONSTITUTION:Since the data information quantities which are written in and read out from a FIFO memory 101 in one period in the cycle of a reference timing pulse 5 are equal to each other, a timing pulse 7 is always outputted to the final burst-like bit, if a frame matching circuit 106 makes normal operations. Therefore, frame matching is performed by using a vacant time slot from the moment when a burst signal train 6 is read out to the moment at which the burst signal train 6 is again read out, when phase absorption, frame matching, and burst conversion are performed on an inputted digital signal train 1 and input timing pulse 2 against the reference timing pulse 5, at which the reference clock 4 and burst signal train 6 of the output side of this converting circuit are to be outputted, by using the FIFO memory 101. |
