| 摘要 |
PURPOSE:To regenerate a clock signal without any phase error by suppressing the phase jitter component of a clock signal due to the pattern of a digital signal when extracting a clock component from the digital signal itself to be transmitted. CONSTITUTION:A base-band quad digital signal is applied from delay circuit 17 to 1st clock extraction circuit 16, composed of clock extraction circuit 2, turning amplifier circuit 5 and limiter 6, and also to discrimination circuit 10 and two sequences of binary signals are regenerated by the regenerating clock signal of voltage control oscillator 9 and outputted to output terminals 18 and 19. Those outputs are converted by binary/quad converter 14 into a quad signal, which is also converted into a local digital signal by transmission-system filter 15. This signal is supplied to 2nd clock extraction circuit 22 as well as circuit 16; and outputs of 1st and 2nd clock extraction circuits are compared by a phase comparator and after the phase jitter component is removed, the output of the comparator is supplied to loop filter 8, where the phase error is removed and applied to circuit 9 as a normal clock. |
