发明名称 |
Method of forming a vertical transistor |
摘要 |
A vertical transistor comprises a semiconductor layer of a first conductivity type having a first doped region (48) formed therein. A second doped region (50) is formed within the first doped region (48). A gate overlies the first doped region such that a low impedance path between the second doped region and the semiconductor layer may be created responsive to a voltage applied to the gate. Isolation regions (38 and 58) are formed through the semiconductor layer to isolate the transistor from other devices.
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申请公布号 |
US5294559(A) |
申请公布日期 |
1994.03.15 |
申请号 |
US19900559756 |
申请日期 |
1990.07.30 |
申请人 |
TEXAS INSTRUMENTS INCORPORATED |
发明人 |
MALHI, SATWINDER |
分类号 |
H01L21/336;H01L21/76;H01L21/762;H01L21/764;H01L21/8234;H01L27/088;H01L29/04;H01L29/06;H01L29/08;H01L29/78;(IPC1-7):H01L21/265 |
主分类号 |
H01L21/336 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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