| 摘要 |
PURPOSE:To reduce the size of a memory cell by locating a thin film transistor above and away from a substrate and equalizing the direction of the placement of its source, channel and drain with that of the data line wiring. CONSTITUTION:An n-channel transistor is formed which uses a n<+> diffusion layer 31 as source connected to a (-) power supply Vss, layer 32 as drain, and a polycrystalline silicon layer 20 as gate. A p-channel transistor is formed which consists of the source 55 connected to a (+) power supply VDD in a polycrystalline silicon layer 22, channel 54, drain 56, and gate of the polycrystalline silicon 20. Both drains are connected with each other through a diode. The direction of the placement of th source, channel and drain on the thin film transistor formed in the polycrystalline silicon layer 22 and 23 is identical with that of the data line wiring. This reduces the size of a memory cell. |
