| 摘要 |
PURPOSE:To attain speed conversion at a common timing and to attain shared returning of each rate by reading and returning bit stream data written in a memory after a prescribed period of time from a writing time regardless of a data rate. CONSTITUTION:The circuit is provided with a memory 1 writing received bit scream data, a decoder 2 decoding data rate information of the bit stream signal, and a delay means 3 receiving decoded data, and reading and reflecting the bit stream data written in the memory 1 after a prescribed period of time from the write time independently of a data rate. In this case, phases (delays) of the bit stream data to be returned are aligned and the speed conversion on a transmitter side is attained at a common timing and the shared returning of each rate is realized. That is, a load value of a frame counter 3 is set to a value corresponding to the data rate to coincide the phases of returned data. |
