发明名称 |
Pseudo-static random access memory |
摘要 |
In a pseudo-static random access memory of the invention, refresh operations are conducted in a normal mode and a self-refresh mode. The memory includes a plurality of bit-line pairs each having two bit lines, a precharge voltage generating circuit for precharging the plurality of bit-line pairs to a first potential level during a precharge period in the normal mode, the circuit being electrically connected to the plurality of bit-line pairs during the precharge period in the normal mode; and bit line discharge circuit for discharging the bit-line pairs during a precharge period in the self-refresh mode, thereby decreasing the potential level of the bit-line pairs to a second potential level which is below the first potential level.
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申请公布号 |
US5289424(A) |
申请公布日期 |
1994.02.22 |
申请号 |
US19920934919 |
申请日期 |
1992.08.25 |
申请人 |
SHARP KABUSHIKI KAISHA |
发明人 |
ITO, NOBUHIKO;IHARA, MAKOTO |
分类号 |
G11C11/409;G11C11/403;G11C11/404;G11C11/406;G11C11/4094;(IPC1-7):G11C13/00 |
主分类号 |
G11C11/409 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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