| 摘要 |
An integrated circuit constructed using exposure and etching steps in an FET fabrication process incorporates electrical lead structures coupled to distributed IC components to compensate for process variation. The electrical lead structure (10,14,16,24,34is composed of an etchable conductive layer constructed in a configuration with graduated coupling widths (B,C,D,E . . . ) forming a graduated range of respective etchable dimensions arranged in an electrically coupled sequence. A primary lead (IA) is coupled at a first end to the widest coupling width (B). A plurality of secondary leads (0B,0C,0D,0E . . . ) distributed along the electrically coupled sequence of graduated coupling widths are coupled respectively to the distributed electrical component elements (P1B,P1C,P1D,P1E . . . ) (N1B,N1C,N1D,N1E . . . ) (RB,RC,RD,RE . . . ) of a distributed electrical component such as a PMOS transistor (P1) NMOS transistor (N1) or resistor (R). The graduated coupling widths (B,C,D,E . . . ) of the electrical lead structure (10,14,16,24,34) electrically couple the secondary leads (0B,0 C,0D,0E . . . ) to the primary lead (IA) through incremental portions of the electrically coupled sequence of graduated coupling widths. The electrical lead structure compensates for variation in exposure and etching steps by varying the number of distributed electrical component elements in the distributed circuit. In a distributed CMOS transistor structure (12) first and second source lead structures (14,16) are oriented to compensate for process variation in length (L) of etchable conductive layer gate segments (G) by varying the number of distributed complementary PMOS and NMOS transistor elements.
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