Interlock acquisition for critical code section execution in a shared memory common-bus individually cached multiprocessor system

摘要

There is disclosed an interlock variable acquisition system and method for use in a processing system of the type including a plurality of processors coupled by a common bus which permits exclusive execution of critical sections by each of the processors while limiting traffic on the common bus. A cache associated with each of the processors stores the value of the interlock variable and locally tests the interlock variable state responsive to an instruction from its processor. If the cache determines that the interlock variable is in the available state, it conveys the available value of the interlock variable to its associated processor and writes, over the common bus, the busy state to each cache associated with the other processors. When its processor completes its critical section, the cache writes, over the common bus, the available state of the interlock variable to each cache associated with the other processors. The other caches update their copies of the interlock variable and do not invalidate them.