| 摘要 |
PURPOSE: To prevent noises in a frequency error signal from causing jitters to a phase of a signal from a variable oscillator by selectively eliminating the frequency error signal from the variable oscillator, when a PLL system reaches a frequency-locked state. CONSTITUTION: A phase error signal, which is fed from a scaler 96 and a frequency error signal fed from a 2's complement circuit 88, are combined by an adder 94 to control a voltage-controlled oscillator VCO 86. The frequency error signal is selectively fed to an adder 94 via a gate circuit 90 controlled by an unlock detector 100. That is, when the PLL system reaches substantially a frequency lock state, the gate 90 inhibits the passing of the frequency error signal. Thus, noises in the frequency error signal fed from the two complement circuit 88 does not cause jitters to a phase from a signal from the variable oscillator. |
