| 摘要 |
<p>PURPOSE:To provide a plural processors system where respective CPU circuits constituting the system are not affected by errorneous data such as omission associated with an abnormal operation. CONSTITUTION:Dual port memories (DPM) 7a, 7b are set to be common storage circuits with one of a main CPU circuit and a slave CPU circuit in the plural processors system. Slave CPU 11a writes data into the data part of DPM 7a at every collection of data from I/0 12a and writes operation information on self CPU 11a into the monitor information storage part of DPM 7a. Main CPU 2 collates to operation information on the monitor information storage part, recognizes the normal operation of slave CPU 11a and reads data from DPM 7a. When slave CPU 11a operates abnormally, main CPU 2 resets slave CPU 11a in the abnormal operation. A watch dog timer 1 monitors only the operation of main CPU 2.</p> |
