发明名称 METHOD AND CIRCUIT FOR RESYNCHRONIZATION OF SYNCHRONOUS SERIES INTERFACE
摘要 <p>PURPOSE: To re-synchronize two devices, without the need of a different line or pin between a controller and a peripheral equipment and without substantially reducing a bit transmission speed. CONSTITUTION: A synchronous serial communication link between a controller 14 and a peripheral equipment 12 is re-synchronized by transmitting a series of the bits of a first logic level by the controller 14. The series of the bits are sufficiently long, so as to decode a command word whose entire bits are the first logic level by the peripheral equipment 12. At the time of decoding the command word, the peripheral equipment 12 resets a synchronization circuit on the inside. Then, the controller 14 transmits the single bit of an opposite logic state and transmits serial data thereafter. At the time of receiving the bit of the opposite logic state, the peripheral equipment 12 releases the synchronization circuit from a reset state and starts the decoding of the serial data which are synchronized with the controller 14.</p>
申请公布号 JPH0646041(A) 申请公布日期 1994.02.18
申请号 JP19930079068 申请日期 1993.03.12
申请人 KURISUTARU SEMICONDUCTOR CORP 发明人 KURIFUTON DABURIYU SANCHIETSU
分类号 H04L7/00;G06F13/42;H04L7/08;H04L7/10;H04L25/40;H04L25/45;H04L29/08;(IPC1-7):H04L7/00 主分类号 H04L7/00
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