| 摘要 |
PURPOSE:To shorten processing time and to simplify software so as to efficiently use hardware resource by sharing registers by means of an arithmetic and logic computing element and an address computing element. CONSTITUTION:At least two independent address computing elements 12 and 13, at least one arithmetic and logic computing element 10 and a register file 11 which is connected to them are provided. The register file 11 is provided with at least two pairs of registers or register pairs which can be used as at least two one-word length registers and which have bit length more than two word length. The arithmetic and logic computing element 10 and the address registers 12 and 13 synchronously operate and execute writing at a clock cycle next to that when input data is read. One arithmetic and logic computing element 10 and two address computing elements 12 and 13 can independently fetch data from the regisiter file 11 and independently write data and therefore the transfer of data is not required. |
