Serial access memory comprising disconnecting circuit between serial bus lines and preamplifier

摘要

An improved serial access memory without erroneous reading where a faster reading operation is required. The serial access memory includes a disconnecting circuit connected between a serial bus line pair and a preamplifier. A data signal read out from a memory cell is provided to the preamplifier via the serial bus line pair. The disconnecting circuit electrically disconnects the serial bus line pair from the preamplifier after a predetermined time has elapsed since the preamplifier commences amplifying operation. An equalize circuit commences equalization of a next data signal right after the operation of the disconnecting circuit. Since the equalize timing of the serial bus line pair for reading the next data is made to commence earlier, proper reading operation can be realized even if the frequency of an externally applied serial out clock signal SOC is increased.