| 摘要 |
PURPOSE:To provide a function for executing double accuracy multiplication at high speed by providing a shifter to generate the input data of an arithmetic operation part by shifting the 2n bit data of an arithmetic operation object to right by (n) bits. CONSTITUTION:Either data ZH, ZL and '0' held in registers 21 and 22 or an arithmetic operation circuit 24 is selected by a multiplexer 23 of an arithmetic operation part 3 and inputted to a shifter 31 and a multiplexer 32. The shifter 31 shifts the input data from the multiplexer 23 to right just for (n) bits and inputs the output to the multiplexer 32. In this case, either the output of the shifter 31 or the output of the multiplexer 32 is selected and inputted to an arithmetic operation circuit 24. At the arithmetic operation circuit 24, the output data of a partial product adder circuit 19 at a multiplication part 1 and the output data of the multiplexer 32 are inputted, the sum of the both is calculated at least, and RH and RL as the arithmetic results are respectively outputted to registers 25 and 26 and the multiplexer 23. |
