| 摘要 |
PURPOSE: To simplify the constitution of a single intersection point type DRAM, to improve the degree of integration and to improve the S/N by enabling to read data of a memory cell and to write data to the memory cell in a bidirectional manner. CONSTITUTION: Row addresses are latched to row decoders 10 and 11 by an external RAS signal, a switching 20 is turned off by the low level of a cell block selection signal IK and a global bit line is divided to upper stages 7 and 8 and lower stages 5 and 6. Switching sections 21 and 30 are turned on by the high level of a selection signals IK, a selected word line WL is made into a high level by the row decoder 11 and the data of a memory cell connected to a bit line 1 are transmitted to a sense amplifier 50 through a bit line 8. Similarly, the data of the cell connected to a bit line 2 are transmitted to a sense amplifier 51 through an SW 21 and a bit line 6. By making the DRAM bidirectional, a switching element normally required between cell columns is not needed and the degree of integration and the S/N are improved. |
