| 摘要 |
The invention i.a. relates to a bit demultiplexing circuit, comprising an internal clock generator which by means of a reference clock generates a number of accurately mutually time delayed clock signals. Clock aligning means are controlled by incoming serial data for providing, by means of the time delayed clock signals, a number of differently phased clock signals, the phase positions of which are set in dependence of said phase position of incoming data. First demultiplexing means clock, by means of said differently phase clock signals, incoming serial data to a parallel data flow. Second demultiplexing means align, by means of one of the differently phased clock signals, this data flow to outgoing parallel data. The invention also relates to a multiplexing circuit and delay line and clock multiplying circuits.
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