发明名称 ACCUMULATOR AND DIGITAL SIGNAL PROCESSOR
摘要 PURPOSE:To execute complicated calculation in a short time by providing a memory to perform computation common to calculation at a time. CONSTITUTION:An adder 10 successively adds input data from an addition input terminal 11 and accumulation intermediate result data from an addition input terminal 12 to finally output the accumulation result from an addition output terminal 13. However, accumulation intermediate result data is a redundant expression where a carry is allowed for each bit, and the accumulation result is the same redundant expression. Consequently, output data obtained through a memory 14 is in a form of the redundant expression, and a carry adder 15 is provided in the output stage for the purpose of converting it to a normal binary expression. Output data is taken out from an output terminal 16 with the normal binary expression by the carry adder 15.
申请公布号 JPH064269(A) 申请公布日期 1994.01.14
申请号 JP19920156741 申请日期 1992.06.16
申请人 SONY CORP 发明人 OKI MITSUHARU
分类号 G06F7/50;G06F17/10 主分类号 G06F7/50
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