| 摘要 |
The low power consuming output buffer circuit is disclosed in which the output of a NOR gate is connected to the gates of a PMOS transistor and an NMOS transistor, the output of a NAND gate is connected to the gates of the PMOS and NMOS transistors, and the drain of the PMOS transistor is connected to the gate of a pull-up transistor and commonly connected to the gate of a pull-down transistor and the drain of the NMOS transistor via the PMOS transistor and NMOS transistor, thereby reducing current flowing via the output buffer.
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