发明名称 Floating point data processing apparatus which simultaneously effects summation and rounding computations
摘要 A data processing apparatus and method for floating point data used in a central processing unit for a digital computer effects the four fundamental arithmetic computations of floating point data and the rounding and normalizing computations. In the case of the floating point addition or subtraction, the mantissa portion of the two floating point data and a generated round addition value are summed using a single adder and, in the case of multiplication, a sum output and a carry output of a multiplying unit and a generated round addition value are added using a single adder, so as to correct the least significant bit of the output of the adder or the round addition value is again added. Since the need of effecting readdition for rounding is small, the average processing step numbers becomes small in comparison with the conventional techniques, and, since the mantissa operation and rounding are effected using the same adder at the same time, less hardware is required.
申请公布号 US5276634(A) 申请公布日期 1994.01.04
申请号 US19910748191 申请日期 1991.08.20
申请人 MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD. 发明人 SUZUKI, MASATO;YASUTOME, MIKAKO;TSURUTA, HIDEYO
分类号 G06F7/50;G06F7/52;G06F7/57;(IPC1-7):G06F7/38 主分类号 G06F7/50
代理机构 代理人
主权项
地址