| 摘要 |
PURPOSE:To increase the operating limit of a synchronization circuit due to deviation of a pulse duty ratio at the input of a high speed clock by using an internal clock having a double period and operating the synchronization circuit in the inside of an LSI with a substantial clock period. CONSTITUTION:An external clock signal CK0 is subjected to 1/2 frequency division by a frequency divider'' circuit 1, from which an internal clock signal CK1 having a double period. The signal CK1 is shaped so that its duty ratio is almost 50% by the 1/2 frequency division by the frequency divider circuit 1. Then the signal CK1 is fed to plural FFs 31Q-3NQ operated at both timings of leading and trailing. As a result, since the plural FFs 31Q-3NQ are operated at both timings of leading and trailing, the operating speed is substantially equal to a drive speed of the FFs 31Q-3NQ at the period of the signal CK0. Thus, the operating limit of the synchronization due to deviation in the duty ratio of the pulse at the input of high speed clock is increased. |
