| 摘要 |
PURPOSE:To efficiently specify the defective part of a memory by preserving the defective part of the memory by a hardware and providing a circuit for reading out the preserved defective part by a central processing unit in a memory control circuit. CONSTITUTION:An error latch part 12 monitors RAS0#, RAS1# signals 13, CAS0H#, CAS0L#, CAS1L#, and CAS1L# signals 14, a WE# signal 15 and a memory address 16. In such a state, when a parity error signal 17 from a parity comparing part 11 becomes active, the error latch part 12 latches a monitoring signal as error information in the inside. To the memory address 16, a row address and a column address are subjected to time division and supplied and the respective addresses are fetched to the inside of the error latch part 12 by the RAS0#, RAS1# signals 13 and the CAS0H#, CAS0L#, CAS1H# and CAS1L# signals 14. |
