| 摘要 |
A state metric quantity memory which enhances processing speed by reconstructing the state metric quantity memory employed in a viterbi decoder for correcting errors created in a digital transmission channel, includes first delay means for storing a previous state metric quantity, second delay means for storing the current state metric quantity, first switching means which operates to make the first delay means store the current state metric quantity, second switching means which operates to make the second delay means store the previous state metric quantities, third switching means connecting the output signals of the first and second delay means to the input terminal of the add compare selector, and fourth switching means for sequentially supplying a clock signal having a basic period so that the first and second delay means store each state metric quantity, thereby reducing delay time of input data and enhancing data processing speed.
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