Logic level converter between CMOS or TTL and current mode logic - provides output with smaller level shift at junction of resistance and chain of two complementary MOSFET(s) with different gate voltages

摘要

A resistance (1) is connected between a source of supply voltage (VCC) and a complementary MOSFET chain (2,3) with gate electrodes returned to different fixed potentials (V1,V2). The potential (V1) applied to the n-channel MOSFET (2) is such that its gate-to-source voltage is always greater than its voltage drop. To set the switching point of the p-channel MOSFET (3) in the region of its input signal level shift, the gate voltage (V2) can be equal to the supply voltage. ADVANTAGE - Relatively large shifts between high and low logic levels can be reduced with use of only one supply voltage source.