Verfahren und Anordnung zum Bilden der Summe einer Kette von Produkten

摘要

In digital signal processing it is often necessary to establish the sum of a chain of products, and to do so as fast as possible. Known signal processors often use two separate data buses for a parallel feed of the values to be multiplied, assuming that these values come from different sources, for example from different memories, and since a product of two binary numbers has double the number of places, an adder with double word length is therefore used. To reduce this substantial outlay with only slight reduction in processing speed, the invention proposes to use an adder with just single word length and to process the most and least significant bits of the product in two successive clock phases such that the values to be multiplied can be simultaneously fed in succession.