Semiconductor RAM with data line and inverted voltage data line - has second p=channel transistor in series with first and connected to one of two inverters

摘要

The voltage of the inverted line (5) is inverted w.r.t. a first data line (4) voltage. There are two transistors (6,7) for selection of a memory element, into which data are written over the first data line, but read-out over the inverted data line. There are two inverters (11,12C), each with a first p-channel transistor (21,22), and a first n-channel transistor (31,32). The input and output of one inverter are linked to the output and input respectively of the other inverter. The inverters are coupled between the source and drain terminal of the first transistor, and the drain and source terminal of the second transistor (7). In series with the first p-channel transistor of one inverter (12C) is connected a second p-channel transistor (42). ADVANTAGE - Facility for reliable simultaneous writing of identical data into all memory elements.