摘要 |
<p>The semiconductor memory device is improved so as to be simplified and to cope with a high speed CPU by allowing the CPU and the memory device (e.g., DRAM) to be controllable by only a single clock. The address control sections (1, 7, 8) are operated on the basis of a monoperiod clock signal CLK and a group of control signals (R/W, CM, RWL, CE and OE). The column address is applied to a plurality of divided memory cell arrays (17 and 18), respectively, so that the memory cell arrays can be interleaved with each other. The input and output buffers (13, 14, 15 and 16) controlled by the input and output control section (1) are operated in pipeline processing, to increase the access speed of data read from or written in the memory cell arrays (17 and 18). <IMAGE></p> |