发明名称 Semiconductor memory device.
摘要 <p>The semiconductor memory device is improved so as to be simplified and to cope with a high speed CPU by allowing the CPU and the memory device (e.g., DRAM) to be controllable by only a single clock. The address control sections (1, 7, 8) are operated on the basis of a monoperiod clock signal CLK and a group of control signals (R/W, CM, RWL, CE and OE). The column address is applied to a plurality of divided memory cell arrays (17 and 18), respectively, so that the memory cell arrays can be interleaved with each other. The input and output buffers (13, 14, 15 and 16) controlled by the input and output control section (1) are operated in pipeline processing, to increase the access speed of data read from or written in the memory cell arrays (17 and 18). &lt;IMAGE&gt;</p>
申请公布号 EP0572026(A2) 申请公布日期 1993.12.01
申请号 EP19930108666 申请日期 1993.05.28
申请人 KABUSHIKI KAISHA TOSHIBA 发明人 WATANABE, YUJI,
分类号 G11C11/407;G06F12/00;G11C5/14;G11C7/10;G11C11/401;G11C11/408;G11C11/409;G11C11/4096;H01L27/10;(IPC1-7):G11C11/409 主分类号 G11C11/407
代理机构 代理人
主权项
地址