发明名称 Memory data synthesizer
摘要 A ROM part (24) of a charactor ROM (21) stores a plurality of font data. A display data RAM (9) simultaneously supplies a plurality of address signals to the charactor ROM (21) which is provided with a plurality of address decoders (25, 26). Respective address signals are decoded by the corresponding address decoders (25, 26), so that the font data corresponding to the address signals are read on the common bit lines (BL1-BLl). Thus, the font data as read are synthesized on the common bit lines (BL1-BLl) as a logical sum.
申请公布号 US5266939(A) 申请公布日期 1993.11.30
申请号 US19910803902 申请日期 1991.12.09
申请人 MITSUBISHI DENKI KABUSHIKI KAISHA 发明人 SHIBASAKI, TAKESHI;KOBAYASHI, HIROSHI
分类号 G09G5/22;G09G5/24;(IPC1-7):G09G3/00 主分类号 G09G5/22
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