发明名称 Circuit arrangement for detection of an erroneous selection signal supplied to selection means
摘要 An erroneous selection signal detecting circuit in a data transfer system. Conventional error detecting systems may not be capable of detecting errors in the selection signal generating circuit using available parity of checksum procedures. The selector means in the present invention selects one of a plurality of input signals on the basis of selection information. This information is applied both to appropriate selection circuits and to two additional selecting circuits also continually receiving fixed data input values. The outputs from these additional circuits are compared to the selection signals through EXCLUSIVE-OR gates, a particular logical indication from the EXCLUSIVE-OR gates indicating a malfunction.
申请公布号 US5267250(A) 申请公布日期 1993.11.30
申请号 US19900627835 申请日期 1990.12.17
申请人 NEC CORPORATION 发明人 UEHARA, IZUSHI
分类号 G06F11/16;H04Q1/22;(IPC1-7):G06F11/00 主分类号 G06F11/16
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