| 摘要 |
PURPOSE: To provide a hyper active detecting and correcting circuit HDC for correcting abnormally high VCO control, and the reset gate of a phase and frequency detector PFD which is not weak to an inside race state. CONSTITUTION: An HDC 50 detects oscillator control by a sensing line 61, and when the oscillator control is increased to an abnormally high level beyond a prescribed limit while a PED 10 does not detect a feedback signal, oscillator reset is signed by the signal line 60. Then, the oscillator control is gradually transmitted through an asynchronous delay line, and the oscillator control is reset to a prescribed reset state. While the oscillator control is reset, the HDC 50 is provided with the monitor of the oscillator control, and when the oscillator control is decreased to the prescribed reset state, the oscillator reset is deasserted. Then, a PLL circuit is normally operated, and locked on to a reference signal. |
