| 摘要 |
PURPOSE:To obtain a synchronization circuit able to be run itself with an input clock signal only so as to continue the synchronization even when an input frame pulse signal is in error for transmission reception of data among plural circuit sections. CONSTITUTION:A change point detection circuit 20 in response to an input clock signal CL detects a leading change point of an input frame pulse signal PF and outputs a change point detection signal OR. An initial value I is set to an N-adic binary counter 14 in response to a load signal AD and the counter 14 counts the signal synchronously with the input clock signal CL and outputs a count CV and outputs a high level ripple carry signal RC for one clock period when the count CV reaches a maximum value N. An inverted gate 16 inverts the ripple carry signal RC and outputs the inverted ripple carry signal IV1. An AND gate 15 ANDs a change point detection signal OR and the inverted ripple carry signal IV1 and gives an AND signal to the N-adic binary counter 14 as the load signal AD. |
