| 摘要 |
<p>PURPOSE:To improve the deterioration of throughput due to a delay jump at the time of pipeline processing. CONSTITUTION:The circuit is provided with a register 12 for inputting and storing a leading address signal 101 for loop processing, a register 13 for inputting and storing a final address signal 102, a counter 14 for inputting and holding a loop frequency data signal 103 and outputting a data signal 108 through a compared result signal 109, a selector 16 for inputting a jumping destination address signal 104 and a data signal 106 and selecting one of the signals 110 through a jump instruction signal 105 to be outputted, an OR circuit 17 for inputting the jump instruction signal 105 and the compared result signal 109 and outputting an OR, a program counter 11 for inputting a data signal 111 inputted from the OR circuit 17 and loading the data signal 110 selected and outputted at the selector 16 and a comparator 15 for inputting a data signal 112 outputted from the program counter 11 and a data signal 107 and outputting the compared result signal 109 through the data signal 108.</p> |
