| 摘要 |
PURPOSE:To eliminate the need for a delay circuit by providing a selection circuit selecting an output of a shift register and an output of a FF between the shift register and each FF while a frequency division clock is used as a control signal. CONSTITUTION:An input data 10 is subjected to retiming at a phase of an input clock 11 by an n-stage shift register 1 and shift data 12-1-12-n are inputted to selection circuits 2-1-2-n. The circuits 2-1-2-n sends the data 12-1-12-n to FF3-1-3-n when the 1/n frequency division clock 13 outputted from a 1/n frequency division circuit 4 is at an H level and sends output data 15-1-15-n of the FF3-1-3-n to the FF3-1-3-n when the clock is at an L level. The FF3-1-3-n applies retiming to select data 14-1-14-n sent from the circuits 2-1-2-n and output the result at the outside of the circuit and then sends it to the corresponding circuit 2-1-2-n. That is, when a clock 12 is at an H level, the FF3-1-3-n output the data 12-1-12-n and keep the preceding state when the clock 13 is at an L level. |
