发明名称 PHASE LOCKED LOOP CIRCUIT
摘要 PURPOSE:To shorten time for designing and producing and to reduce the cost by digitally processing the prevention of an oscillating operation stop in VCO. CONSTITUTION:A digital phase error signal corresponding to phase difference between an input signal (a) taken out by a phase comparator circuit 11 and a comparison signal is converted into an analog signal by a voltage converting circuit 12 so as to be impressed on a voltage control oscillation circuit (VCO) 13 as a control voltage. VCO 13 supplies the output oscillation frequency to a phase conparator circuit 11 through a frequency divider circuit 14 as the comparison signal. A control circuit 20 permits the phase comparator circuit 11 to stop an operation at the time of digitally detecting that the repeated frequency of the input signal (a) becomes equal to below a setting value and permits the phase comparator circuit 11 to output the digital phase error signal of a high impedance or a specified value.
申请公布号 JPH05304468(A) 申请公布日期 1993.11.16
申请号 JP19920107752 申请日期 1992.04.27
申请人 FUJITSU LTD 发明人 TOKUKANUSHI HIDETAKA
分类号 H03L7/14 主分类号 H03L7/14
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