| 摘要 |
<p>PURPOSE:To attain the resetting operation of a digital circuit without executing special purpose operation in the case of holding the state of the digital circuit by fixing the logical state of an operation clock and stopping the oscillation of an oscillation circuit at the time of power off. CONSTITUTION:Since an SD signal is in a high level at the time of normal operation, a master clock MCLK is oscillated by an oscillation circuit connected to a COSO and a COSI and a part including a NAND gate 221. At the time of power off, the SD signal is turned to a low level, the MCLK is fixed at a high level and the contents of a static RAM or the like in the device are held. When a RES2 signal is turned to a high level, reset operation such as operation for turning each terminal state in the device to a voltage level suppressing a current flow into the terminal is executed, and simultaneously the address specifying operation of a ROM address control part 105 is fixed. At the time of turning on the power supply again, the SD signal is returned to the high level, the MCLK restarts oscillation, and after the lapse of a prescribed time, the RES2 signal is returned to the low level and the operation of the device is restarted.</p> |
