| 摘要 |
Digital system which generates the different clock signals with two or more crystals, detects the phase difference and compensates the detected phase difference. This circuit compensates the phase difference per unit of 1 byte, 1 frame and 1 block. This system blocks include the 1st, 2nd crystals (10,20) which drive F1,F2 oscillating outputs, an 1/M division circuit (40) which divides F1 signal into 1/M divided signal, an 1/N division circuit (60) which outputs F2 signal, a 1st phase detection circuit (70) which generates 1st compensated signal, a 2nd phase detection circuit (80) which generates 2nd compensated signal, and a 1st phase compensation circuit (30) and 2nd phase compensation circuit (50).
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