Frequency synthesizer using phase-locked loop.

摘要

In a phase locked loop frequency synthesizer having multiple feedback loops, a reference phase signal (frx) is developed into two signals (fr) each having a frequency half that of the reference frequency and the phase difference of these two signals is a half wavelength. The output frequency produced by a voltage-controlled oscillator (6) is divided by two frequency dividers (12,13) in accordance with predetermined frequency divisions factors. Each of the frequency-divided signals (fp) and each of the developed signals (fr) are subjected to phase comparison in pairs. A voltage signal corresponding to the phase differences is fed through a low-pass filter (5) and supplied to the voltage-controlled oscillator. The pulse modulation imposed on the voltage-controlled oscillator is thus reduced and the loop response time is improved by implementing an increased number of phase comparisons. <IMAGE>