发明名称 |
Power integrated circuit with latch-up prevention. |
摘要 |
<p>A power integrated circuit includes a substrate with an overlying epitaxial surface layer of opposite conductivity type. A semiconductor power device, such as a high-power diode or lateral MOS transistor, is located in the epitaxial layer and forms a p-n junction diode with the substrate. The power integrated circuit also includes a separate semiconductor well region in the epitaxial layer, in which one or more low-power semiconductor circuit elements are formed. In order to minimize the problem of latch up in the low-power circuit elements due to the injection of minority carriers from the substrate, the power integrated circuit is provided with a collector region and an isolation region between the power device and the well region having the low-power circuit elements.</p> |
申请公布号 |
EP0566186(A2) |
申请公布日期 |
1993.10.20 |
申请号 |
EP19930201002 |
申请日期 |
1993.04.06 |
申请人 |
PHILIPS ELECTRONICS N.V. |
发明人 |
SIN, JOHNNY;SINGER, BARRY;MUKHERJEE, SATEYNDRANATH |
分类号 |
H01L27/04;H01L21/822;H01L27/02;H01L27/092;(IPC1-7):H01L27/02 |
主分类号 |
H01L27/04 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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