| 摘要 |
PURPOSE:To reduce the power consumption of the dinamic semiconductor memory in its refresh operation. CONSTITUTION:A memory cell array is divided into a plurality of memory cell arrays 9a, 9b, column decoders 7a, 7b, word drive circuits 8a, 8b and sense amplification circuits 11a, 11b are arranged respectively at the memory cell arrays 9a, 9b. Control signals PHIa, PHIb for executing a refresh operation which is matched to a memory cell at the minimum data holding time of the individual memory cell arrays 9a, 9b are generated by using an internal control-signal generation circuit 3. Thereby, the memory cell arrays 9a, 9b are refreshed. |
