发明名称 SEMICONDUCTOR INTEGRATED CIRCUIT AND DELAY TIME ADJUSTMENT METHOD FOR THE SAME
摘要 PURPOSE:To attain fine-adjustment of a delay time by connecting plural capacitors in parallel or in series via fuses. CONSTITUTION:The total capacitor capacitance being a combined capacitance of capacitors connected in series or in parallel is adjusted by selectively blowing out 1st stage fuses F111, F112,...F11m, F11(m+1),...F11n, 2nd stage fuses F141, F142,...F14m, F14(m+1),...F14n, and 3rd stage fuses F131, F132,...F13m, F13(m+1),...F13n so as to change number of capacitors or connection form connected electrically to a signal line 13. Since lots of total capacitance values are set over a wide range, fine-adjustment of the delay time is easily implemented.
申请公布号 JPH05268013(A) 申请公布日期 1993.10.15
申请号 JP19920063502 申请日期 1992.03.19
申请人 发明人
分类号 H01L21/82;G11C11/4076;H01L21/822;H01L27/04;H03K5/13;H03K5/133 主分类号 H01L21/82
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