发明名称 CLOCK GENERATOR
摘要 PURPOSE:To improve the performance of a clock generating section in a feedforward system time axis correction circuit. CONSTITUTION:The generator consists of a reference clock generator 10, a variable delay circuit 11 comprising CMOS gates outputting a delay phase connected in multi-stage, and a phase comparator 12 detecting a deviation in a delay time generated by temperature fluctuation or the like of the delay circuit 11. An application power supply voltage to the CMOS gates 111-11n is generated by superimposing a control signal generated from a detected phase through an LPF 13 onto a reference power supply voltage by a voltage comparator 15. Thus, the delay time is adjusted and a phase being equal divisions of one clock period is generated.
申请公布号 JPH05268017(A) 申请公布日期 1993.10.15
申请号 JP19920060528 申请日期 1992.03.17
申请人 发明人
分类号 H03K5/135 主分类号 H03K5/135
代理机构 代理人
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