Electronic divider circuit - contains gate circuit system combined with tetrade subtraction cicruit

摘要

The circuit forms the division result subtractively and processes the two numbers digit-serially using a tetrade subtraction circuit (11). The tetrade subtraction circuit is combined with a gate circuit system (10). The two digits of each of the two numbers are fed into the tetrade subtraction circuit and the resulting subtraction result digit simultaneously fed into a dividend residue memory chain. Each digit is stored in its correct partial stage of the memory chain. USE/ADVANTAGE - The divider circuit is based on a special subtraction circuit which does not process the input numbers with clock-controlled shift registers but with a gate circuit system combined with a tetrade subtraction circuit.