Process for fabricating multiple pillar trench capacitor for DRAM.

摘要

A method is disclosed for fabricating a DRAM trench capacitor with multiple-pillars inside the trench for increased surface area. A thin pad oxide (12) of a few tens of nonometers is grown on a silicon substrate (10). A layer of silicon nitride (14) is deposited and another layer of oxide (16) is then deposited. Then a layer of polysilicon (18), a layer of nitride (20), and a layer of large-grained polysilicon (22) are deposited sequentially. Then, the trench is defined by a lithographic mask (24) and the exposed large-grained polysilicon (22) is etched in CF4. Since CF4 etches the polysilicon and nitride (20) at almost the same rates, the topographical features existed in the polysilicon layer (22) is copied to the nitride layer (20). The nitride layer is partially etched. The RIE etching gas is then changed to a mixture of HBR, SiF4, Helium, and NF3 which gives a very directional polysilicon etching with a good selectivity to nitride and a very high selectivity to oxide. Consequently, the topographical features on the nitride layer (20) is enhanced and is transferred to the polysilicon layer (18) which is used as a mask to etch the oxide (16) nitride (14) and pad oxide (12) to form pillars. Using the polysilicon material left as a mask, the CVD oxide, nitride, and pad oxide are sequentially etched in a mixture of CF3H and CO2 which etches nitride and oxide with a good selectivity to polysilicon and silicon substrate. Next, the lithographical mask is removed and the silicon substrate is etched. The portion of the three polysilicon-nitride-polysilicon layers is now exposed and is removed leaving behind only the CVD oxide layer. The CVD oxide, nitride, and pad oxide on top of the resultant silicon pillar are removed by wet etching the pad oxide in a buffer HF. The pillars are then recessed below the silicon substrate level using silicon-etching RIE, the CVD oxide 16 is removed in BHF or RIE, an oxide-nitride-oxide (ONO) layer is grown and deposited as a capacitor interdielectric, and polysilicon 28 is deposited and chemical-mechanically polished using the nitride layer as stopping layer.