发明名称 BINARY COMPLEMENT UNIT
摘要 PURPOSE:To obtain the complement unit of simple constitution which maintains the relation of negative-to-positive conversion without fail. CONSTITUTION:Data input terminals for (n) bits are coupled with (n) bits of one side of an adder 14 through inverters, the output side of a NAND circuit 15 is coupled with the least-digit input terminal CO among input terminals for (n) bits of the other side of the adder 14, and the remaining inputs are grounded; and the largest-digit input terminal E3 among the input terminals of the NAND circuit 15 is coupled with the largest digit A3 of (n)-bit data, other terminals are coupled with the output sides of the inverters except the largest digit in order, and a complementary number is obtained from the output terminals for (n) bits of the adder 14. For example, when negative maximum values 1, 0, 0, and 0 are inputted as 4-bit input data, they are inverted and 0, 1, 1, and 1 are inputted to the adder; and thus 0, 1, 1, and 1 are outputted for the input of 1, 0, 0, and 0, and consequently the negative-to-positive conversion is performed.
申请公布号 JPH05257643(A) 申请公布日期 1993.10.08
申请号 JP19920086225 申请日期 1992.03.10
申请人 发明人
分类号 G06F7/38 主分类号 G06F7/38
代理机构 代理人
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