| 摘要 |
PURPOSE:To provide a codec without the characteristic deterioration of an S/N due to an asynchronous noise and with low power consumption suitable to incorporate into an IC, etc. CONSTITUTION:A reception timing generation circuit 50 with a simple circuit configuration is provided instead of a conventional reception PLL circuit. At the circuit 50, a D/A conversion timing signal S50 is generated based on a clock signal S30c outputted from a transmission PLL circuit 30, and a reception digital signal fetch completion signal S61a outputted from a reception controller 61. A D/A converter 62 converts a digital signal Di fetched at the reception controller 61 to an analog signal based on the signal S50, and it is sent to a reception filter 63. The reception filter 63 outputs an analog signal Ao by performing filter processing on the output of the D/A converter 62 based on a clock signal 30b supplied from the transmission PLL circuit 30. |
