| 摘要 |
PURPOSE:To reduce the adjustment error at the time of adjusting the free run frequency of a PLL by connecting an attenuator between a phase comparator and a VCO, thereby decreasing a phase error signal to 1/n. CONSTITUTION:The phase of an input signal via an edge detection circuit 2 and the phase of an output signal of a VCO 5 via a BPF 6 are compared by the sample-hold circuit 7 of a phase comparator of a PLL and the free-run frequency of the PLL is automatically adjusted. The attenuator 8 is connected between the circuit 7 and the VCO 5 and the gain of a phase error signal is set to 1/n. Thus, the offset of a capture range due to the field-through of an analog switch in the circuit 7 or the like is reduced to 1/n and the frequency adjustment error is reduced. |
