发明名称 Method for the hierarchical comparison of schematics and layouts of electronic components
摘要 The present invention takes advantage of the hierarchical nature of the design to perform a hierarchical comparison on as many blocks and sub-blocks which can be matched between the layout and the logic design. Because the internal connections were previously verified when the first occurrence of the block was compared, repetition of lengthy comparisons of multiple occurrences of the same blocks in the designs is avoided and subsequent comparisons are performed simply by comparing the input and output connections to the block.
申请公布号 US5249133(A) 申请公布日期 1993.09.28
申请号 US19910684047 申请日期 1991.04.10
申请人 SUN MICROSYSTEMS, INC. 发明人 BATRA, PRADEEP
分类号 G06F17/50 主分类号 G06F17/50
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