发明名称 CLAMP CIRCUIT
摘要 PURPOSE:To apply the circuit even for a use requiring a high speed operation by adopting the configuration of no capacitive load interposed in a feedback loop and using a cascode amplifier. CONSTITUTION:An inverting input terminal of a differential amplifier 1 is connected to a signal line. Cascode connection is adopted for the clamp circuit, in which an output of the differential amplifier (basically common emitter transistor(TR)) 1 is received by a grounded-base amplifier 2. Only an emitter follower 3 is interposed in a feedback loop and the circuit is not affected by the mirror effect. The emitter follower 3 implements only push or pull of a current as the nonlinear operation. When a potential at an inverting terminal of the differential amplifier 1 is lower than a potential at a noninverting terminal, an output of the cascode amplifier comprising the differential amplifier 1 and the grounded-base amplifier 2 goes to a high level (positive). Thus, a charging current flows from the emitter follower 3, the potential at the inverting terminal of the differential amplifier 1 is raised to OV and then clamped.
申请公布号 JPH05251970(A) 申请公布日期 1993.09.28
申请号 JP19920047097 申请日期 1992.03.04
申请人 YOKOGAWA ELECTRIC CORP 发明人 SUGIHARA YOSHINOBU;TACHIHARA HIROYUKI
分类号 H03G11/00;H04N5/16 主分类号 H03G11/00
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